In wireless communications, due to large variations in received signal power caused by propagation attenuation (e.g., fading due to buildings or geographic features), a control mechanism referred as automatic gain control (AGC) has to be used in a receiver to control the gain of the receiving amplifier dynamically so that subsequent sections can operate within a desired operating range. These sections include amplifiers, mixers, analog-to-digital converters (ADC), and baseband analog or digital processing devices. An AGC circuit is designed to keep the amplified received signal at a near-constant level over a large dynamic range of received signal power levels. The parameters involved in designing an AGC circuit include its operational range and its response time.
In some communication systems, the signal variation can exceed 80 to 90 dB in signal power. This wide variation range could be caused by hills or buildings and power control failure occurring when a mobile station is in close proximity to a base station. It is desirable for an AGC circuit to be able to operate in a very wide range so that the communication system can work in many scenarios.
In package-switched wireless communications, AGC has to setup on every package. The more time for setting up AGC, the less time available for transmitting data. Therefore, the effective data transmission rate will be reduced. The problem is more obvious and serious when the transmission rate is very high. With a faster AGC circuit, a communication system will have more time to transmit data and therefore increase its capacity.
In a wireless communication system, the power consumption is one of the major concerns. In order to make the communication system to work for longer time with the same battery, every subsystem including AGC should consume as less power as possible.
One technology to make an AGC circuit to have wide operational ranges is given by U.S. Pat. No. 4,263,560, entitled. LOG-EXPONENTIAL AGC CIRCUIT, by Dennis W. Ricker. FIG. 1 is a digital implementation diagram of the AGC based on Ricker's patent.
The digital AGC circuit shown in FIG. 1, generally denoted by 100, utilizes both the logarithmic algorithm and exponential algorithm. The input signal Sin is applied to a variable-gain amplifier 110. The output of the variable-gain amplifier is converted into digital signal Sout by an ADC device 120. The digital signal Sout will be sent to digital envelope detector 130 and other devices such as automatic frequency control and clock recovery for further processing. The output of the envelope detector 130 is the envelope of the signal represented by Sout. This envelope, denoted by X, is applied to a logarithmic device 140 with its output connected to the negative terminal of an adder 160. The reference signal level R, after going through a logarithmic device 150, is connected to the positive terminal of adder 160. The output of adder 160 is the error signal E. This error signal is applied to an integrator 170 to filter out the high frequencies of the error signal. The output of integrator 170, denoted by K, then goes through an exponential device 180. The output of exponential device 180 is digital gain control signal G. This digital gain control signal is converted into analog gain control signal by a digital-to-analog converter (DAC) 190. Finally, the analog gain control signal controls the amplification factor of the variable-gain amplifier 110.
There are some problems with the digital AGC of FIG. 1 when it is applied in package-switched high-speed wireless communication systems.
One problem associated with the digital implementation is hardware consuming and time consuming. First, a lot of hardware is needed to build circuits to approximate both logarithmic function and exponential function. Second, a lot of time is needed for the circuits to complete the calculation of logarithmic function and exponential function. The more hardware and more time will lead more power consumption and reduce effective data rate in package-switched high-speed wireless communications.
Another problem is associated with signal strength. When the incoming signal is very strong, there is distortion on the output of variable-gain amplifier and therefore the output of digital envelope detector will not correctly reflect the signal strength. In the digital implementation, there is an extra problem. The signal after ADC could be limited even if the signal before ADC is not. When the incoming signal is very strong, the output of ADC does not correctly reflect the coming signal strength due to the operational range limitation of an ADC circuit. Due to quantisation error of ADC, there is some discrepancy between input and output of an ADC. When the incoming signal is very weak, this discrepancy could be very significant considering the relatively small incoming signal.
Using the notations on FIG. 1, mathematically, one can obtainE((n+1)T)=1n(R)−1n(X(n+1)T)K((n+1)T)=K(nT)+α·E((n+1)T)G((n+1)T)=eK((n+1)T)where E is the error signal, R is the reference signal level, X is the envelope, K is the output of integrator, G is the gain, T is the clock cycle of gain adjustment, the nT is the moment of the nth clock cycle, and α is the adjusting coefficient embedded in the integrator 170. α is a positive number and usually much smaller than 1.
Further, one can deriveG((n+1)T)=G(nT)·(R/X((n+1)T))αOrG((n+1)T)=G(nT)·β·(X((n+1)T))−α  (1)with β=Rα.
Therefore, the gain adjusting factor F isF=β·X−α  (2)